Introduction
Consider a 200 MHz state analyzer with a setup/hold specification of 3 ns and clock offset resolution of +/-500 ps. Assuming perfect alignment of clock to data, the circuit under test must have a data valid window of at least 3 ns for the logic analyzer to be able to capture reliable data. Perfect alignment is not likely. Clock offset increments of +/- 500 ps may shift the entire setup and hold window too far to be of use. To be useful, the clock offset resolution must be much smaller than the data valid window. Clock offset resolutions of 50 ps are available from Agilent Technologies.

Data Valid Window
To make reliable measurements with a state analyzer, the setup and hold window of the logic analyzer must be smaller than the data valid window, and the resolution of the clock offset adjustment must allow you to place the analyzer setup and hold window inside the data valid window.

This Interactive applet illustrates the relationship between the logic analyzer's setup and hold window and the circuit under test's data valid window. The setup time is shown in yellow, while the hold time is shown in yellow/green. Manipulate the four parameters shown to determine if a reliable measurement can be made. The "Clock Offset" parameter allows you to horizontally shift the clock trigger. You can increase or decrease the setup and hold times by adjusting the appropriate scrollbar. The "Data Valid Window" allows you to adjust the width of the data valid window.

Note: This applet works best in Netscape 3.0+

View the applet

Real-world devices require time for the data at inputs to become valid (setup time) and time for gates to act on the data (hold time). Setup and hold times are specified as minimum requirements for receiving devices. Transmitting devices must have a window of valid data large enough to allow for the setup/hold specifications of receiving devices and an extra margin for signal integrity effects.

For circuits operating above 50 MHz, effects that reduce the data valid window include: system noise, edge rates, coupling from signals in dense layouts, variations in propagation delays across signals in buses, reflections, and ringing.

Usable Sample Rate of a State Analyzer
In tight circuits, the data valid window can be nearly equal to the setup and hold window of receiving devices. Circuit designs with small data valid windows require the designer to select a state analyzer with specifications compatible with the data valid window. Table 1 lists the clock periods, setup/hold specifications, and percent of clock period for setup/hold specifications from several systems under test.

Table 1: Systems under Test with Percent Clock Period Used by Setup/Hold Specifications

Consider your circuit under test when selecting a state analyzer. A state analyzer with a setup and hold window equal to or less than receiving devices in the circuit will provide the most reliable measurements. Remember, the usable maximum sample rate of a state analyzer is limited by setup/hold and not just maximum clock frequency. (Target specific probes designed with comparators and registers compatible with the system under text can provide improved performance for state analyzers.) Table 2 shows examples of the limits on the maximum usable sample rate related to the percent of clock period for setup/hold specifications.

Table 2: Setup/Hold Specification Related to Maximum Usable Sample Rate of Percent of Clock Period

How Sampling Techniques Affect a State Analyzer's Setup and Hold Specification
What makes up the setup and hold specification of your state analyzer? That depends on how your state analyzer acquires data. There are two basic methods of acquiring data, synchronous and asynchronous. At first this may seem to be an oxymoron. How can a state analyzer sample asynchronously? Isn't the purpose of a state analyzer to be in sync with the target clock?

Some logic analyzers use an asynchronous sampler to make state measurements. By sampling asynchronously and then aligning the external clock to the nearest asynchronous sample a pseudo state analyzer is created. Both sampling methods will have a setup and hold specification that includes channel-to-channel skew and an uncertainty factor. The uncertainty factor includes effects such as sample aperture windows, channel-to-channel coupling within the analyzer, temperature effects, frequency effects, jitter, and analyzer noise.

Asynchronous sampling has an extra limiting component. Asynchronous acquisition is limited to a minimum setup and hold specification of twice the period of the sampling clock. As an example, an asynchronous sampler running at 2 Gs/s will have a minimum setup and hold window of 2 x 500 ps = 1 ns.

Synchronous acquisition latches the data sampled and produces the smallest possible setup and hold window for a logic analyzer because asynchronous sampling frequency is not a factor. In other words, if all other components of the setup and hold specification are equal, a 2 Gs/s asynchronous sampler will have a 1 ns wider setup and hold window than a synchronous sampler clocked at 2 Gs/s. Figure 1 provides setup and hold time formulas for asynchronous and synchronous sampling.

Figure 1. Setup and Hold Time Formulas for Asynchronous and Synchronous Sampling.

Typical Versus Worst-Case Scenarios
Designers need to be aware of the difference between typical and worst case state analyzer specifications. A typical specification can be very misleading. Does it mean that the specification is valid at room temperature 98% of the time, or 51% of the time? Is the typical specification only true for minutes after a calibration? Ask your vendor about the specifics of any typical specifications. Your state analyzer is your reference. You need to rely on what it tells you.

a) Temperature drift. Temperature drift affects placement accuracy. Measurements are taken at temperature extremes (such as 0º and 50º). Variations and shifts in the setup and hold window are recorded.

b) Frequency effects. The possibility exists for worse results at different frequencies due to standing waves or reflections, either on the probe cables or internally. State analyzers are tested across different frequencies.

c) Channel-to-Channel coupling. Measurements are taken with adjacent data channel edges switching opposite directions simultaneously, or with random timing of adjacent edges switching.

d) Multiple modules. Measurements must be specified across the maximum number of modules configurable into a single machine.

Conclusion
Designers rely on the accuracy of their tools. Troubleshooting high-speed circuits is hard enough without chasing measurement problems from unreliable or inaccurate test equipment. When choosing a state analyzer for high-speed measurements, select a state analyzer with the setup and hold, sampling rate, and positioning resolution specifications that meet your needs. Key issues to consider include your system clock rate and the setup/hold specifications of your receiving devices.